1. Field of the Invention
Embodiments of the present invention generally relate to device architectures. More specifically, the present invention relates to devices, e.g., memory devices, having spare input-output lines and to methods of using such devices.
2. Description of the Related Art
High reliability computers are often required in critical missions for medical, financial, and military applications. Such computers usually include processors and memory devices that manage and manipulate data to achieve mission objectives. Memory devices typically have input-output (I/O) lines that connect to memory “cells” that are organized into arrays. Such memory devices further include support circuitry that can access the individual memory cells by memory addresses and that can WRITE data into and READ data from addressed memory cells. Memory devices are often categorized by how wide their I/O ports are. Common memory device port widths are 4, 8, and 16 lines, which enables 4, 8, or 16 data bits to be input/output at a time.
Due to inherent processing limitations, it is not uncommon for one or more memory cells to be faulty. While a memory device may contain millions of memory cells, if even one memory cell is faulty the memory device is defective. To address this problem some memory device manufacturers have included “redundant” memory cells that can be selectively used to repair faulty primary memory cells. Such repairs have been made by selectively activating “fuses” that are disposed in the memory device. Whenever a fuse is opened, routing logic accesses a redundant memory cell or array of redundant memory cells instead of the defective primary memory cell.
Although redundant memory cells are useful in improving manufacturing yields, even after manufacture memory devices can fail. Most failures are caused by a single bit error that results from the failure of a single memory cell or associated banks of memory cells. Logic is often utilized to detect faulty memory cells, typically during memory initialization e.g., during power-on or following a reset. When a memory cell is found faulty the memory address associated with that memory cell (or cells) is marked as “bad” and not used. Unfortunately, the computer may crash or become unusable until the failed memory device can be replaced. Such problems are simply not acceptable in mission critical systems.
One approach to improving reliability is to implement memory I/O with error correcting Code (ECC) capabilities. While this can greatly enhance reliability by enabling error correction and detection, additional memory to store the error correcting code is required. By using error correction and detection a defect on any particular I/O line can be found and corrected. Error correcting more than one I/O line, while possible, becomes fairly complicated and requires more memory. Typically, error correction is limited to one line while error detection is limited to two lines.
While common memory device port widths are 4, 8, and 16 lines, modern high-end processors have 32 or 64 (or greater) bit wide ports. To accommodate such port widths, memory devices are often arranged into memory modules. FIG. 1 illustrates a typical prior art dual-inline memory module (DIMM) 100 that is used to supply memory for a 64-bit wide processor. The DIMM 100 includes 5 memory devices, the memory devices 102, 104, 106, 108, and 110 that are mounted on a circuit card 112. All of the memory devices are x16 (have 16 I/O lines). All of the I/O lines of the memory devices 102, 104, 106, 108 connect to DIMM contacts 116. Those memory devices provide 64 I/O port connections for the processor (which is not shown). The memory device 110 only connects 8 of its 16 I/O lines to the DIMM contacts 116. As shown, the other 8 I/O lines 120 are unused. Thus, DIMM 100 provides 72 I/O lines while 8 I/O lines are unused and represent wasted potential. While all I/O connections are shown in FIG. 1, in practice both sides of the DIMM 100 have contacts.
Therefore, a system architecture that makes use of unused I/O lines would be beneficial. Also beneficial would be a device architecture that enables a system supplier to make use of all available I/O pins. Also beneficial would be memory devices that enable a system designer to correct a memory system for defects.